======================SPICE_MODEL_NOTES=========================== ==================VAF_and_Base===================================================== We design engineers tend to find the same surprises in our first silicon over and over again. This is the first of several emails which will address the most common problems encountered. It is very common to hear a design engineers say that the first silicon's gain is for some reason signifcantly lower that the simulations. The gain of a transistor is for now defined by a single Early voltage value. VAF = 1/(percent_shift_per_volt) An Easy way to understand VAF is to think in terms of current tolerance percentages. A current increase 1% per volt the the early voltage is 1/1% = 100. likewise a 2% coresponds to 50. Early voltage and the "Available_gain" of a transistor are almost the same thing. Available_Gain_Bipolar = VAF/vt ... Gain_Mos = VAF/( N*vt ) For bipolar transistors, the maximun effective gain is found by dividing early voltage by thermal voltage as shown above. By thinking in terms of N, the same is also true for MOS transistors. So a NPN Early voltage of 26 should give out a gain of 60dB. ^ ^ /_\ +5V /_\ +5V _|_ _|_ / _ \ / _ \ \/ \/ | \/ \/ High Indepedance /\_/\ V /\_/\ \___/ tail \___/ | current | ^ __|_______ | /_\ | | | ______| _ <- -> _ |_|'Q5 | Open Loop Gain? |-|_|/PNP PNP\|_|+| | |`-> _| |_| |`_ _'| |_| | |_|' Q6 ___ |_ | | |`->_____|Out| | |_____||___| | |___| | | || | | | | | | | | _______| | ___|_____ |_|'Q3 | | | _| | _| |`-> __| |___/\ ___ |_|'Q1 |_|'Q2 |_|'Q4 <== \/ | |`-> |`-> |`-> gain _|_ NPN |________|_________| stage /// _|_ /// Gnd The typical Opamp is shown above. Say you wanth an open loop gain of 120dB. Typically there is a main gain stage ( Q4 ) which provides most of the gain. In this case Q3 is being used as a voltage buffer to the base of Q4. Since Q3 is buffering the collector of Q2, The input gm stage may have a gain in the 60dB range too. Together there may be 120dB. The actual available gain and early voltage for a BiCMOSabi min geometry npn is give below. Early Voltage BiCMOS_NPN Voltage driven Available Gain 50 _______________________________________________ | . . . . . | 45 |.....................2mA.......................| 64.8dB | . . 300uA . 300uA . . | 40 |..............2mA.............2mA..............| | . . . . . | 35 |...........300uA..................300uA........| 62.5dB | . . . . . | 30 |.........2mA..........................2mA......| | . . . . . | 25 |......300uA..............................300uA.| 59.7dB | . . . . . | 20 |......2mA......................................| | . . . . . | 15 |....300uA......................................| 55.2dB | . . ________________________ | 10 |....2mA..........| VAF = 1/(Slope_Ic/Ic ) |....| | . . |________________________| | 5 |.300uA.........................................| 45.7dB | . . . . . | 0 |__2mA__________________________________________| 0 1V 2V 3V 4V 5V 6V Collector Volage The early voltage above appears to be insensitive collector current, and this could be VERY MISLEADING. Say the voltage buffer for Q4 is removed and now the base of Q4 is seeing the output of the input transconductance stage. By having the base now be driven with a current source, a different set of curves are measured. ^ ^ /_\ +5V /_\ +5V _|_ _|_ / _ \ / _ \ \/ \/ | \/ \/ High Indepedance /\_/\ V /\_/\ \___/ tail \___/ | current | ^ __|_______ | /_\ Open Loop Gain? | | | ______| _ <- -> _ |_|' | | |_|/PNP PNP\|_| | | |`-> _| |_| |`_ _'| |_| | |_|' ___ |_ | | |`->_____| | | |___ _||__| | |___| ___|_____ | | || | | | _| | _| | __| |___/\ ___ |_|'Q1 |_|'Q2 |_|'Q4 <== \/ | |`-> |`-> |`-> gain _|_ NPN |________|________| stage /// _|_ /// Gnd At low currents there tends to be a "soft breakdown" which is hidden if the base of the transistor is voltage driven. NPN_300uA Early Voltage 50 _______________________________________________ | . . . . . | 45 |.......................V.......................| | . . V . V . . | 40 |..............VI...............V...............| | . . I . . . | 35 |..........I............I...........V...........| | . . . . . | 30 |......VI...............................V.......| | . . . I . . | 25 |.....V....................................V....| | . . . . . | 20 |....I..........................I.............V.| | V . . . . . | 15 |...................................I...........| | . . . . . | 10 |...V..................................I........| | . . . . . | 5 |...I......................................I..I.| | . . . . . | 0 |__V____________________________________________| 0 1V 2V 3V 4V 5V 6V At higher collector currents there is less "soft breakdown", but "soft sat" will be present. Voltage driving the base appears to hide both of these details. NPN_2mA Early Voltage 50 _______________________________________________ | . . . . . | 45 |.......................V.......................| | . . . . . | 40 |...............V...............V...............| | . . . . . | 35 |..........................I....I...............| | . . I . . | 30 |..........V........................I...V.......| | . . I . . . | 25 |......................................I........| | . . . . . | 20 |.......V.......I...............................| | . . . . . | 15 |...............................................| | . I . . . . | 10 |....V..........................................| | . . . . . | 5 |.......I.......................................| | . . . . . | 0 |__V____________________________________________| 0 1V 2V 3V 4V 5V 6V In the circuit where Q4 is driven from a current source, aspect 0f "soft sat" and "soft breakdown" will be defining the open loop gain. So a single value for the early voltage does not provide enough information. The regular curve tracer plot also makes it difficult to see the gain of the transistor. Soft_sat Curve_tracer Soft_breakdown ............................................... | . . . . . | | . . . . . *| 3m |.........................................*.....| | . * * * * * * * . | | * . . . . *| 2m |......*....................................*...| | * .* * * * * * * * * | | * *. . . . . | 1m |...*..........................................*| | * * * * * * * * * * * | | * . . . . . | 0 |*______________________________________________| 0 1V 2V 3V 4V 5V 6V If the curve tracer curve is math processed to yield either Early_voltage or Available_gain as a function of collecter voltage , then it would be much easier to see whether a design is close to being in trouble. Early_Voltage BiCMOS_NPN Current driven Available Gain 50 _______________________________________________ | . . . . . | 45 |_____________.100uA............................| 64.8dB | NO SOFT_SAT | . . ________________| 40 |_____________|300uA...........| LESS BREAKDOWN | | 100uA . 300uA . |________________| 35 |..........................2mA..2mA.............| 62.5dB | . . . . . | 30 |......300uA........100uA...........2mA.........| | . . 2mA . . . | 25 |..100uA..................300uA........2mA......| 59.7dB | . . . . . | 20 |.....300uA....2mA....100uA...300uA.......2mA...| | . . . . ___________ | 15 |.100uA...................100uA..| BREAKDOWN |..| 55.2dB | . 2mA . . .|___________| | 10 |..300uA...__________..........100uA...300uA....| | . | SOFT_SAT | . . . | 5 |......2mA|__________|...............100uA......| 45.7dB | . . . . . | 0 |__V____________________________________________| 0 1V 2V 3V 4V 5V 6V collector voltage If we could convince the Fab to take Available_Gain curves, we would know how much room needs to added to allow for process variations. This might save us all some time fighting yield problems. Thinking also in terms of transistor gain in dB may also be of value. (especially for MOS) It is not obvious how the vbic models can be made to match both the voltage driven mode and current driven modes at the same time. The vbic models have both softsat and breakdown terms. But the accuracy range may be very limited in terms of collector current range. Given the +/-10dB gain variations in the curve above, it it not hard to see why gain differences always come out in first silicon. We probably need to know the gain of a transistor over a collector current range and over 6 months in production. For now the TC of the VAF appears to be well defined. IS_and_NF doping levels in silicon define diode voltage of pn junction. higher doped junction higher diode voltage ^ +5V /_\ | _|_ Apply / _ \ VBE = NF*(KT/q)*ln(I/Is) 100uA \/ \/ = 0.026*ln(I/Is) | /\_/\ | \___/ Doping defines Is V ______| | _| + | |' NPN |___| Measure VBE |`-> _ | _|_ /// If NF =1 factor of ten at junction tranlates to 60mV. ^ gumbal - pooh /_\ _ | _-- / <== slope =1/2 <= IR DROP IKF_| - / | ic / / | / / ib slope =1 =1/NF Beta = ic/ib | / / | / _- |/_-- <== slope =1/NE NE =1.5 <= Leakage | |_______|\ VBE |/ IS and NF terms define a transistor's Vbe under most conditions. At high current TR drop causes deviation from diode equation At low current leakage causes deviation from diode equation BF bipolar transistor always consists to two pn junctions. normal mode of operation, emitter base junction forward biased while collector base junction is reverse biased. In spice model,BF refer to beta in forward bias condition This is always the emitter base junction. ^ +5V /_\ ___|____ _|_ ___|__ Apply / _ \ | | Measure 100uA 1uA \/ \/ | DVM | | | /\_/\ | | | | \___/ |______| V V | | | _| hfe = Beta = 100uA/1uA =100 | |' NPN |___| Ratio Doping defines Bf |`-> | _|_ /// BR In spice model, both pn junctions are measured and modeled. BR VAR etc define behaviour of junction reverse biased (collector base is on). Most these parameters except BR have mild effects on transistor behaviour. ^ +5V /_\ ___| _|_ Apply / _ \ Measure Open Collector 1uA \/ \/ | /\_/\ ___ | \___/ | | + set by BR V | |___| | _| 60mV | |' NPN |___| |`-> - | _|_ /// When collector is open, both pn junction will be forward bias. processes like VIP2 two junctions are close enough in doping emitter bas junction close to collector base that the open collect is almost at ground. for most processing doping levels of collector base much lighter collector base junction voltage typically 60mV less. spice BR term can be adjusted to match silicon open collector. VAF When measure beta, collector base voltage effect mag of beta. ^ +5V ^ 0-> +5V /_\ /_\ ___| ______| _|_ ___|__ Apply / _ \ | | Measure 100uA 1uA \/ \/ | DVM | | | /\_/\ | | | | \___/ |______| V V | | | _| hfe = Beta = 100uA/1uA =100 | |' NPN |___| Ratio Doping defines Bf |`-> | _|_ /// "Early voltage" can be though of as the inverse of tolerance of collecter current verus collector voltage. A VAF of 100 means 1% increase in collector current over 1volt. ^ I collector /_\ | | 300uA _| ____----- 3uA = ib | / | /_____------ 2uA | / | /______-------- 1uA |/___________________|\ Vcollector |/ transistor curves slightly slope up because as collector base reverse bias voltage is increased, base gets slightly smaller ========================IKF_and_ISE_and_NE================================= All transistors naturally have a point where athey are having trouble putting out the power. When the current gets high enough, regions in the base region have too much IR drop and start turning off. At this point, the beta of the transistor starts dropping very quicky. The spice term that models this is IKF. It is something like were the beta begins to drop. Typically, the output transistors of an amplifier need to be made large because of this effect. NE defines low I beta drop off 100 ............................................ | . . . . . . . | | . . . . . beta . | | . . . beta . . . beta | 10|.....................................:......| | . . . . . . . : . | | . . beat . . . . : . | | . . . . . . . : . | 1 |________beta_________________________:______| 10pA .1nA 1nA 10nA .1unA 1uA 10uA .1mA: 1mA 10mA : ^ /_\ IKF ____________| When you plot beta versus collector current, you will see the beta also drop off at low collector current. In fact, this is the way you can tell how well a transistor is processed. When the silicon has very few defects, leakage currents are very low. Such a transistor will still have a fair amount of beta at very low currents. NE defines low I beta drop off 100 ............................................ | . . . . . . . | | . . . . . beta . | | . . . beta . . . beta | 10|............................................| | . .beta. . . . . . | | . . . . . . . . | | . . . . . . . . | 1 |________beta________________________________| 10pA .1nA 1nA 10nA .1unA 1uA 10uA .1mA 1mA 10mA ^ /_\ |________ ISE and NE In the spice model, the processing impacts on beta are modeled as the ISE term which defines where the beta drops and the NE term which defines how fast the beta drops. ========================RB_and_RBM_and_IRB_and_RE======================== As expected, all pn junctions has internal resistances. This will be the main reason why a diode will not always increase 60mV per factor of ten increase in emitter current. As current flows thru the RB and RE spice terms shown below, there will of course be IR drop. ^ +5V /_\ | _|_ / _ \ VBE = (KT/q)*ln(I/Is) \/ \/ _ /\_/\ RB /| \___/ _/\/ ______| | /\/ _| + | |' NPN |_______| Measure VBE |`-> RE _ |__/\ ___ \/ _|_ /// The resistance at the base "Rb" drops as current current increases. This happens around the same current where the beta also drops. At higher currents, only the base regions which have low base resistance tend to stay on. In spice, RB represent the base resistance at low current, RBM is the base resistance at high current, and IRB is the current were the base resistance begins to drop. ========================RC================================= ^ +5V /_\ ___|_______________ _|_ _|_ Apply / _ \ / _ \ 100uA \/ \/ \/ \/ | 1mA | /\_/\ /\_/\ | | \___/ 60mV RC \___/ V V | ____/\ ____| | _| \/ _|_ | |' NPN | | |___| |___| |`-> | _|_ /// The collector region also has some resistance. The spice term is RC. For the circuit above, if the RC value is 200 ohms, the collector voltage should have 200mV of IR drop in the collector resistance in addition to the 60mv will the collector voltage will be when open. In this case, the collector voltage will be 260mV. ========================TF_and_CJE_and_IRF======================== The term FT for "F_sub_tau" is the way processing people like to rate the speed of their transistors. FT is defined as { how high does the frequency have to get before the AC beta drops to one}. npn FT about 1/(2*pi*TF) 10GHz ................................................. | . . . __ IKF . | . . . | . 1GHz |.....................................V.......... | Re*Cje . . 1/3ns . . | | . . .1/3ns . 100MHz |......|.............1/3ns.....1ns....1ns........ | V . 1ns . 1/3ns . | 1ns . . . 10MHz |.....1/3n................................1ns.... | . . . . 1ns . . . . 1MHz |_______________________________________________. 1uA 10uA 100uA 1mA 10 mA A typical FT versus collector current is shown above. This FT terms really is a measument of the "transient time" across the base region. Heavy light Very Light ___________________________ | :+|-:Base:-| + : | Emit :+|-: P :-| + : Collect | N :+|-:n :-| + : N | :+|-:nn :-| + : | p:+|-:nnn :-| + : | pp:+|-:nnnn:-| + : |______:_|_:____:_|___:_______ <- -> holes electrons The processing people try and make the thickness of the base region as thin as possible so it takes an electron little time to travel across it. The depletion region in the emitter base also defines Cje. Since the doping is usually high, the thickness of the depletion region is thin, and therefore the Emitter base Junction capacitance cannot be ignored. ___ |(C)| |___| | |_____________ NPN _|_ Schematic / _ \ for FT \/ \/ /\_/\ \___/ ___ emitter/base Ic | |(B)|___________________ | | |___| | | _|_ | V _|_Cje _|_Cde \ / | ___ ___ _v_ | |100fF | |If/Bf | |______|________|__________| | _|_ |(E)| |___| In the spice models, the TF for "forward transient time" is modeled as a capacitor Cde. This "capacitor" increases as more current flow through the emitter base junction, because the more forward biased a pn junction is, the thinner is the emitter base junction. The impedance of the emitter base junction also drops. At low currents, Cde is small, the impedence of the emitter base diode is large. The FT is defined in this region as were the junction capacitance Cje shorts out the AC current which would otherwise go into the emitter base diode. At high enough collector current, the Cde is large enough and emitter base junction resistance low enough that Cde and emitter base junction impedance dominate the speed. The spice term TF defines Cde and therefore FT. npn FT about 1/(2*pi*TF) 10GHz ................................................. | . . . __ IKF . | . . . | . 1GHz |.....................................V.......... | Re*Cje . . 1/3ns . . | | . . .1/3ns . 100MHz |......|.............1/3ns.....1ns....1ns........ | V . 1ns . 1/3ns . | 1ns . . . 10MHz |.....1/3n................................1ns.... | . . . . 1ns . . . . 1MHz |_______________________________________________. 1uA 10uA 100uA 1mA 10 mA When the beta starts to crash, the speed is also degraded as well. From the processing people's point of view,the emitter base junction capacacitance {Cje}, defines the speed at low currents. At higher currents, speed is defined by the transient time { TF } through the base thickness. And there will be a current level {IKF} above which both beta and speed are degraded. ========================CJX_and_VJX_and_MJX_and_ETC======================== From the design engineers view point, there is a little more going that needs to be considered. Every pn junction affect the high speed performance. The full schematic is shown below. ___ |(C)| |___| | ____________________|____________________ | | _|_ _|_Cjs | | / _ \ ___ | | \/ \/ | _|_Cjcx _|_Cjc /\_/\ _|_ ___ ___ \___/ \sub/ ___ | Rbb | Ic | \ / |(B)|_|_/\ __|_______________ | | V |___| \/ | | _|_ | V (hidden) _|_Cje _|_Cde \ / | ___ ___ _v_ | |100fF | |If/Bf | |______|________|__________| | _|_ |(E)| |___| All of these junction capacitors also change over voltage. This is where the VJX and MJX terms come into play. The other speed parameters ar listed below. Various things like collector voltage and current affect speed in other ways. XCJC = fraction of cb cap connect to internal base node PTF = excess phase at ft ^ Tff /|\ | / |______________/ |__________________\ IKF / IKF = Q_Bo/Tau_Bf Knee current TF = 1/(2*PI*Ft) TF = tf(1+xtf*(icc/(icc+itf))^2 *exp(vbc/1.44vtf)) ITF = high cuurent point for tf .01 vip2 VTF = voltage effecting tf 1.5 vip2 XTF = coeff of bias on tff 10 vip FC = Fbias nonideal junc-capcoeffi 0.5 F_tau BiCmos npn vs Collector Voltage. 7GHz ................................................ | 3 3 . . . . | 32 2 2 3 . . . 6GHz |..3........2.....3.............................. | 2 . 2 3 . . . | 3 . 2 . 3 . . 5GHz |.2....................2...........3............. | 2 . . 2 . . |3 . . . . 4GHz |3............................................... | . . . . | . . . . 5GHz |_______________________________________________. 0 1mA 2mA 3mA ========================XTB_and_EG_and_XTI======================== Two major things change over temperature. The diode voltages all have a large Temperature coeoffecient around -2mV/C_deg. This value needs to be defined well in order to make voltage band gap reference. The spice model parameter which defines that is XTI. XTI defines TC of diode, expect 3/n Model now uses XTI = 5.6 Is(T2) [ Is(T1)*(T2/T1)^(XTI) ]*... ...*[ exp( (-q*Eg(300)/kT2)*(1-T2/T1) ) ] The Beta can also drop a factor of two at low temperatures. This is modeled with the spice parameter XTB BF(T2) = BF(T1)*(T2/T1)^XTB XTB = 2 BiCMOS_pnp 58% @(-45C/27C) 2.4 = V3_pnp 53% 2.1= V2_pnp Sometimes models have Temperature coeffecient values for all the resistors as well. This may greatly slow down simulations while not providing much improvement in accuracy. Is up to the designer. ========================Noise_Terms======================== The new 442 environment claims to have better noise features than before. Given the crossover to the new environment, it may be worth while to take another look at noise modeling. I have included below a model file I am testing on the perfect 10 process to see what it takes to get the models and silicon to give me the same results. This is not meant to knock the modeling group. It seems like constant vigilance is required for processing. And design has always played the row of QA anyway. I am trying to get my model checkers to be a bit more easier to use, and I am trying to make it easier to measure silicon as well. { Coyote } The more eyes we can get looking at everything, the better. ... Don Sauer ^ gumbal - pooh /_\ _ | _-- / <== slope =1/2 <= IR DROP IKF_| - / | ic / / | / / ib slope =1 =1/NF Beta = ic/ib | / / | / _- |/_-- <== slope =1/NE NE =1.5 <= Leakage | |_______|\ VBE |/ ======================DESCRIPTION_UNITS=========================LIMITS============ NMOS_IMPACT_ION Measure Substrate Current This test measures to effect of hot electrons which create substrate current and degrade the lifetime of a MOS device. ___ Vds =5V | 2 | |___| Ibs Measure Substrate Current ___ _| -> ___ | 3 |___||_________ | 1 | This test measures to effect of |___| || | |___| hot electrons create substrate ||-> |____| current degrade lifetime of _|_ _|_ a MOS device. Vgs =0->5V | 4 | /// |___| Vbs =0V EFFLN Measures the effective channel length as defined by Poly CD and N+ source/drain of a minimum N-channel transistor. VTNs are measured on each of the three transistors; drain currents are measured with the gate voltage set at VT+0.5, and drain at 0.1 V. A linear regression is performed using the inverse of the drain currents vs. the drawn L sizes (.8, 1.6, 3.2) and the x-intercept is obtained; this is DELTAL. This value is then subtracted from the ideal minimum layout dimension (0.8) to give EFFLN_8__B. ^ Ids /|\ | / | / |________/_______\ Channel Length ^ / |__ Eff_L Lamda = (L_eff +Delta_L)/L_eff = 1+Delta_L/Leff Lamda = Delta_L/L_eff = Delta_L/(L_drawn-Ldef) L_drawn-Ldef =Delta_L/(Lamda) L_drawn_2 -L_drawn_1 = Delta_L/(Lamda_2)-Delta_L/(Lamda_1) Delta_L = (L_drawn_2 -L_drawn_1)*Lamda_2*Lamda_1/(Lamda_1-Lamda_2) ________________________________________________________ | L_eff=(L_drawn_2 -L_drawn_1)*Lamda_2/(Lamda_1-Lamda_2) | |________________________________________________________| NMOS_BODY_EFFECT IDS=1u Measure body effect [Vto(2.5V)- Vto(0V)] This test defines the effect the bulk voltage has on the thresshold voltage of a channel. Affects common mode turn on voltages of switches. Checks device sensitivity to P- well biasing and "body effect". The result from VTN40X_8_B is compared to a new VT measurement with the P- well biased at -2.55 V. The delta between the two is BEFFN_8__B, which formerly was referred to as M-factor. ___ ___ Vd = .1V |(D)| Vd = .1V |(D)| |___| |___| ___ _| ___ _| Vgate_1 |(G)|____||____ |(G)|____||_____ |___| ||Ê | |___| || | ||-> \|/gnd ||-> \|/ "NMOS" | V "NMOS"| V -2.55V _|_ Vgate_2 _|_ |(S)| |(S)| |___| |___| ______________________ |Vgate_2 -Vgate_1 =~ M | |______________________| NMOS_BREAKDOWN_V Measure Drain voltage needed for 1uA This test defines the maximum supply voltage for this process. ___ | | Vds =0 -> 20V |___| | ___ _| V IDS ___ | |___||_________ | | |___| || | |___| ||-> |____| Vgs=0V _|_ _|_ | | /// |___| Vbs =0V NMOS_LEAKAGE Measure Ids at Vg =0 Measure turn off drain current This test defines how much supply current will flow in a logic device which is in a DC state. (DC supply current) ___ | | Vds = 5V |___| | ___ _| V IDS ___ | |___||_________ | | |___| || | |___| ||-> |____| Vgs=0V _|_ _|_ | | /// |___| Vbs =0V NMOS_THRESHOLD__V Measure Ids vs Vgs to extrapolate Vt Slope defined by Overdrive voltage ___ Vds =0.1V | | |___| | IDS ___ _| V ___ | |___||_________ | | |___| || | |___| ||-> |____| Vgs 0->3V _|_ _|_ | | /// |___| Vbs =0V ^ Ids /|\ | / Ids = .1V*Beta*Vod | / |_______-________\ Vg ^ / |__ Vt ^ Ids /|\ ...Vgate_2 | / \...Vod | /....Vgate_1 / | / |_______-________\ Vg ^ / |__ Vt ___ ___ Vd = .1V |(D)| Vd = .1V |(D)| |___| |___| ___ Vg_1 _| ___ _| |(G)|____|| Ids |(G)|____|| 2Ids |___| ||-> | |___| ||-> | "NMOS" | V "NMOS"| V _|_ Vg_2 _|_ |(S)| |(S)| |___| |___| Ids = .1V*Beta*Vod Ids*2= .1V*Beta*(Vod*2) Vg_2 -Vg_1 = Vod __________________ |Vth =~ Vg_1 - Vod | |__________________| contact potential V (KT/q)*ln(A) 680mV = E+20 660mV= E+19 V_fermi_p (KT/q)*ln(N_accept/ni) V_fermi_n (-1)*(KT/q)*ln(N_donor/ni) Breakdown BVbco_V 95*(rho_epi_ohm_cm)^(.722) BVceo_V BVbco_V/( (Beta_max+1)^(.25) ) BVbco_thickLimited_V 36*(w_um)^(.861) ------------------------------------------------------- mobility u_0*T^(-3/2) due to lattice scattering Resistance (ohms/square) versus doping 100 ................................................ | p . . . . . . | |n . . . . . . | | n . . . . . . | | . . . . . . | 10|....n..p........................................| | . . . . . . | | . p . . . . . | | .n . . . . . | | . . . . . . | 1|..........n...p.................................| | . . . . . . | | . . p. . . . | | . .n . . . . | | . . . . . . | .1| ................n.......p......................| | . . . . . . | | . . . n . . . | | . . . . p . . | | . . . n. . . | .01|...............................n..p.............| | . . . . . . | | . . . . .n . | | . . . . . p . | | . . . . . p | .001|.........................................n......| | . . . . . . n | | . . . . . . p n| | . . . . . . p | | . . . . . . p| .0001|________________________________________________| E14 E15 E16 E17 E18 E19 E20 E21 doping( /cm^3) Mobility (cm/sec)*(cm/V) versus doping ................................................. | . . . . . . | | . . . . . . | | . . . . . . | |e e . . . . . | 1000 |.............e..................................| | . . . . . . | | . . . . . . | | . . e . . . | | . . . . . . | |h...h...........................................| | . h . . . . . | | . . h . .e . . | | . . . . . . | | . . . . . . | 100 |.........................h.........e............| | . . . . . e e | | . . . . . . | | . . . . h . . | | . . . . . h h | |................................................| | . . . . . . | | . . . . . . | | . . . . . . | | . . . . . . | 10 |________________________________________________| E14 E15 E16 E17 E18 E19 E20 E21 doping( /cm^3)