==========================DIGITAL_PINOUTS============================= ______________ | O | ___|___ |___ 1 |___| _|_ 14 VCC |___| 14 ___| \S/ ___|___ 2 |___|___O _|_ |___| 13 ___|___ \S/ |__ 3 |___| _|_ O___|___| 12 ___| \S/ ___|___ 4 |___|___O _|_ |___| 11 ___|___ \S/ |___ 5 |___| _|_ O___|___| 10 ___| \S/ ___|___ 6 |___|___O _|_ |___| 9 ___| \S/ |___ 7 |___|GND O___|___| 8 | INV+SMIT | |______________| ----------------------------------------------------------------------------------------- ______________ | O | ___| |___ 1 |___|____ 86 VCC |___| 14 ___|__ | |___ 2 |___| |x| ____|___| 13 ___| |\_/| | __|___ 3 |___|__\_/ |x| |___| 12 ___| |\_/| |___ 4 |___|____ \_/__|___| 11 ___|__ | |___ 5 |___| |x| ____|___| 10 ___| |\_/| | __|___ 6 |___|__\_/ |x| |___| 9 ___| |\_/| |___ 7 |___|GND \_/__|___| 8 | XOR | |______________| ----------------------------------------------------------------------------------------- ______________ | O | ___| |___ 1 |___|____ 32 VCC |___| 14 ___|__ | |___ 2 |___| | | ____|___| 13 ___| |\_/| | __|___ 3 |___|__\_/ | | |___| 12 ___| |\_/| |___ 4 |___|____ \_/__|___| 11 ___|__ | |___ 5 |___| | | ____|___| 10 ___| |\_/| | __|___ 6 |___|__\_/ | | |___| 9 ___| |\_/| |___ 7 |___|GND \_/__|___| 8 | OR | |______________| ----------------------------------------------------------------------------------------- ______________ | O | ___| |___ 1 |___|____ 08 VCC |___| 14 ___|__ | |___ 2 |___| _|_|_ ____|___| 13 ___| \___/ | __|___ 3 |___|___| _|_|_ |___| 12 ___| \___/ |___ 4 |___|____ |___|___| 11 ___|__ | |___ 5 |___| _|_|_ ____|___| 10 ___| \___/ | __|___ 6 |___|___| _|_|_ |___| 9 ___| \___/ |___ 7 |___|GND |___|___| 8 | AND | |______________| ----------------------------------------------------------------------------------------- ______________ | O | ___| |___ Y4 |___| 1 4051 16 |___| VCC ___| |___ Y3 |___| 2 15 |___| Y2 ___| |___ COM |___| 3 14 |___| Y1 ___| |___ Y7 |___| 4 13 |___| Y0 ___| |___ Y5 |___| 5 12 |___| Y3 ___| |___ INH |___| 6 11 |___| A ___| |___ VEE |___| 7 10 |___| B ___| |___ GND |___| 8 9 |___| C | MUX | |______________| ----------------------------------------------------------------------------------------- ______________ | O | ___| |___ Y0 |___| 1 4052 16 |___| VCC ___| |___ Y2 |___| 2 15 |___| X2 ___| |___ COMY |___| 3 14 |___| X1 ___| |___ Y4 |___| 4 13 |___| COMX ___| |___ Y1 |___| 5 12 |___| X0 ___| |___ INH |___| 6 11 |___| X3 ___| |___ VEE |___| 7 10 |___| A ___| |___ GND |___| 8 9 |___| B | MUX | |______________| ----------------------------------------------------------------------------------------- ______________ | O | ___| |___ IN/OUT_A |___| 1 4016 14 |___| VCC ___| |___ IN/OUT_A |___| 2 13 |___| CNTL_A ___| |___ IN/OUT_B |___| 3 12 |___| CNTL_D ___| |___ IN/OUT_B |___| 4 11 |___| IN/OUT_D ___| |___ CNTL_A |___| 5 10 |___| IN/OUT_D ___| |___ CNTL_A |___| 6 9 |___| IN/OUT_C ___| |___ VEE |___| 7 8 |___| IN/OUT_C | SWITCHES | |______________| ----------------------------------------------------------------------------------------- ______________ | O | ___| 4007 |___ 1 |___|-|| ||-|___| 16 ___|P||_ ____||P|___ 2 |___|_|| | | ||_|___| 15 ___| | | |___ 3 |___|____| |,----<-|___| 14 ___| | || _||P|___ 4 |___|-||_| || |||_|___| 13 ___|N|| || |___|___ 5 |___|_|| || ==== |___| 12 ___|______||_|N | |___ 6 |___| | |_|___| 11 ___| ===== |___ 7 |___|____| N |_____|___| 10 | | |______________| ----------------------------------------------------------------------------------------- ______________ | O | ___| |___ _OutEnable |___| 1 374 20 |___| VCC ___| |___ OUT0 |___| 2 19 |___| OUT7 ___| |___ Din0 |___| 3 18 |___| Din7 ___| |___ Din1 |___| 4 17 |___| Din6 ___| |___ OUT1 |___| 5 16 |___| OUT6 ___| |___ OUT1 |___| 6 15 |___| OUT5 ___| |___ Din1 |___| 7 14 |___| Din5 ___| |___ Din3 |___| 8 13 |___| Din4 ___| |___ OUT3 |___| 9 12 |___| OUT4 ___| |___ GND |___| 10 11 |___| Clk_Pulse | D FF | |______________| ----------------------------------------------------------------------------------------- MM54C85/MM74C85 4-Bit Magnitude Comparator ______________ | O | ___| |___ INPUT B2 |___| 1 85 16 |___| VCC ___| |___ INPUT A2 |___| 2 15 |___| INPUT A3 ___| |___ OUTPUT A=B |___| 3 14 |___| INPUT B3 ___| |___ INPUT A>B |___| 4 13 |___| OUTPUT A>B ___| |___ INPUT AB AB AB3 X X X X X X H L L A3B2 X X X X X H L L A3=B3 A2B1 X X X X H L L A3=B3 A2=B2 A1B0 X X X H L L A3=B3 A2=B2 A1=B1 A0Q7 Reset (Clear) L X X L L-L H l l L q0 ->q6 Shift H l h L q0 ->q6 H h l L q0 ->q6 H h h H q0 ->q6 H(h) e HIGH Voltage Levels L(l) e LOW Voltage Levels X = Immaterial qn = Lower case letters indicate the state ofreferenced input or outputone setup time prior toLOW-to-HIGH clock transition. Pin Names Description A, B Data Inputs CP Clock Pulse Input (Active Rising Edge) MR Master Reset Input (Active LOW) Q0->Q7 Outputs 'F164A a high-speed 8-bit serial-in/parallel-out shift register. Serial data entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears register, setting all outputs LOW independent of the clock. The 'F164A is a faster version of the 'F164. Features Typical shift frequency of 90 MHz Asynchronous Master Reset Gated serial data input Fully synchronous data transfers Guaranteed 4000V min ESD protection 'F164A is a faster version of the 'F164 F164A is an edge-triggered 8-bit shift register with seri- al data entry and an output from each of eight stages. Data entered serially through two inputs (A or B); either of these inputs can be used as active HIGH En- able for data entry through the other input. unused input must be tied HIGH. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q 0 logical AND of the two data inputs (A # B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides other inputs and clears register asyn- chronously, forcing all Q outputs LOW. Mode Select Table Operating Inputs Outputs Mode MR A B Q0 Q1->Q7 Reset (Clear) L X X L L-L H l l L q0 ->q6 Shift H l h L q0 ->q6 H h l L q0 ->q6 H h h H q0 ->q6 H(h) e HIGH Voltage Levels L(l) e LOW Voltage Levels X = Immaterial qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Pin Names Description A, B Data Inputs CP Clock Pulse Input (Active Rising Edge) MR Master Reset Input (Active LOW) Q0->Q7 Outputs ----------------------------------------------------------------------------------------- UP/DOWN MODULO-16 BINARY COUNTER ______________ | O | ___| |___ P1 |___| 1 193 16 |___| VCC ___| |___ Q1 |___| 2 15 |___| P0 ___| |___ Q0 |___| 3 14 |___| MR ___| |___ CPD |___| 4 13 |___| TCD ___| |___ CPU |___| 5 12 |___| TCU ___| |___ Q2 |___| 6 11 |___| PL ___| |___ Q3 |___| 7 10 |___| P2 ___| |___ GND |___| 8 9 |___| P3 | | |______________| Function Table MR PL CPU CPD Mode H X X X Reset (Asyn.) L L X X Preset (Asyn.) L H H H No Change L H _/ H Count Up L H H _/ Count Down H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial _/ = LOW-to-HIGH Clock Transition Pin Names Description CPU Count Up Clock Input (Active Rising Edge) CPD Count Down Clock Input (Active Rising Edge) MR Asynchronous Master Reset Input (Active H) PL Asynchronous Parallel Load Input(ActiveLO) P0->P3 Parallel Data Inputs Q0->Q3 Flip-Flop Outputs TCD Terminal Count Dow (Borrow)Output(ActiveLO) TCU Terminal Count Up (Carry)Output(Active LO) Function Table. The Terminal Count Up (TC U ) and Terminal Count Down (TC D ) outputs are normally HIGH. When the circuit has ----------------------- ______________ | O | ___|___ |___ 1 |___| _|_ 14 VCC |___| 14 ___| \S/ ___|___ 2 |___|___O _|_ |___| 13 ___|___ \S/ |__ 3 |___| _|_ O___|___| 12 ___| \S/ ___|___ 4 |___|___O _|_ |___| 11 ___|___ \S/ |___ 5 |___| _|_ O___|___| 10 ___| \S/ ___|___ 6 |___|___O _|_ |___| 9 ___| \S/ |___ 7 |___|GND O___|___| 8 | INV+SMIT | |______________| ______________ | O | ___| |___ 1 |___|____ 86 VCC |___| 14 ___|__ | |___ 2 |___| |x| ____|___| 13 ___| |\_/| | __|___ 3 |___|__\_/ |x| |___| 12 ___| |\_/| |___ 4 |___|____ \_/__|___| 11 ___|__ | |___ 5 |___| |x| ____|___| 10 ___| |\_/| | __|___ 6 |___|__\_/ |x| |___| 9 ___| |\_/| |___ 7 |___|GND \_/__|___| 8 | XOR | |______________| ______________ | O | ___| |___ 1 |___|____ 32 VCC |___| 14 ___|__ | |___ 2 |___| | | ____|___| 13 ___| |\_/| | __|___ 3 |___|__\_/ | | |___| 12 ___| |\_/| |___ 4 |___|____ \_/__|___| 11 ___|__ | |___ 5 |___| | | ____|___| 10 ___| |\_/| | __|___ 6 |___|__\_/ | | |___| 9 ___| |\_/| |___ 7 |___|GND \_/__|___| 8 | OR | |______________| ______________ | O | ___| |___ 1 |___|____ 08 VCC |___| 14 ___|__ | |___ 2 |___| _|_|_ ____|___| 13 ___| \___/ | __|___ 3 |___|___| _|_|_ |___| 12 ___| \___/ |___ 4 |___|____ |___|___| 11 ___|__ | |___ 5 |___| _|_|_ ____|___| 10 ___| \___/ | __|___ 6 |___|___| _|_|_ |___| 9 ___| \___/ |___ 7 |___|GND |___|___| 8 | AND | |______________| ______________ | O | ___| |___ Y4 |___| 1 4051 16 |___| VCC ___| |___ Y3 |___| 2 15 |___| Y2 ___| |___ COM |___| 3 14 |___| Y1 ___| |___ Y7 |___| 4 13 |___| Y0 ___| |___ Y5 |___| 5 12 |___| Y3 ___| |___ INH |___| 6 11 |___| A ___| |___ VEE |___| 7 10 |___| B ___| |___ GND |___| 8 9 |___| C | | |______________| ______________ | O | ___| |___ Y0 |___| 1 4052 16 |___| VCC ___| |___ Y2 |___| 2 15 |___| X2 ___| |___ COMY |___| 3 14 |___| X1 ___| |___ Y4 |___| 4 13 |___| COMX ___| |___ Y1 |___| 5 12 |___| X0 ___| |___ INH |___| 6 11 |___| X3 ___| |___ VEE |___| 7 10 |___| A ___| |___ GND |___| 8 9 |___| B | | |______________| ------------------------------------------------------------- MM54C85/MM74C85 4-Bit Magnitude Comparator General Description ______________ | O | ___| |___ INPUT B2 |___| 1 85 16 |___| VCC ___| |___ INPUT A2 |___| 2 15 |___| INPUT A3 ___| |___ OUTPUT A=B |___| 3 14 |___| INPUT B3 ___| |___ INPUT A>B |___| 4 13 |___| OUTPUT A>B ___| |___ INPUT AB AB AB3 X X X X X X H L L A3B2 X X X X X H L L A3=B3 A2B1 X X X X H L L A3=B3 A2=B2 A1B0 X X X H L L A3=B3 A2=B2 A1=B1 A0B3 X X X X X X H L L A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L A3 B, A < B and A - B), and three outputs (A > B, A < B and A - B). This device compares two four-bit words (A and B) and determines whether they are ``greater than,' `less than,'or`equal to' each other by high level on appro- priate output. words greater than four-bits,units can be cascaded by connecting the outputs (A > B, A < B, and A - B) of the least significant stage to cascade inputs (A < B, A > B and A - B) of the next-significant stage. In addition least significant stage must have a high level voltage (V IN(1) ) applied to A < B input and low level voltage (V IN(0) ) applied to A > B and A < B inputs. Features Wide supply voltage range 3.0V to 15V Guaranteed noise margin 1.0V High noise immunity 0.4 V CC (typ.) Low power fan out of 2 TTL compatibility driving 74L Expandable to `N' stages Applicable to binary or BCD Low power pinout: 54L85/74L85 TRUTH TABLE Comparing Inputs Cascading Inputs Outputs A3,B3 A2,B2 A1,B1 A0,B0 A>B AB AB3 X X X X X X H L L A3B2 X X X X X H L L A3=B3 A2B1 X X X X H L L A3=B3 A2=B2 A1B0 X X X H L L A3=B3 A2=B2 A1=B1 A0Q7 Reset (Clear) L X X L L-L H l l L q0 ->q6 Shift H l h L q0 ->q6 H h l L q0 ->q6 H h h H q0 ->q6 H(h) e HIGH Voltage Levels L(l) e LOW Voltage Levels X = Immaterial qn = Lower case letters indicate the state of referenced input or outputone setup time prior to LOW-to-HIGH clock transition. Pin Names Description A, B Data Inputs CP Clock Pulse Input (Active Rising Edge) MR Master Reset Input (Active LOW) Q0->Q7 Outputs 'F164A is a high-speed 8-bit serial-in/parallel-out shift register. Serial data entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent the clock. The 'F164A is a faster version of the 'F164. Features Typical shift frequency of 90 MHz Asynchronous Master Reset Gated serial data input Fully synchronous data transfers Guaranteed 4000V min ESD protection 'F164A is a faster version of the 'F164 F164A edge-triggered 8-bit shift register with seri- al data entry and output from each of eight stages. Data entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH En- able for data entry through other input. An unused input must be tied HIGH. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q 0 logical AND of the two data inputs (A # B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears register asyn- chronously, forcing all Q outputs LOW. Mode Select Table Operating Inputs Outputs Mode MR A B Q0 Q1->Q7 Reset (Clear) L X X L L-L H l l L q0 ->q6 Shift H l h L q0 ->q6 H h l L q0 ->q6 H h h H q0 ->q6 H(h) e HIGH Voltage Levels L(l) e LOW Voltage Levels X = Immaterial qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Pin Names Description A, B Data Inputs CP Clock Pulse Input (Active Rising Edge) MR Master Reset Input (Active LOW) Q0->Q7 Outputs ------------------------------------------------------------- UP/DOWN MODULO-16 BINARY COUNTER ______________ | O | ___| |___ P1 |___| 1 193 16 |___| VCC ___| |___ Q1 |___| 2 15 |___| P0 ___| |___ Q0 |___| 3 14 |___| MR ___| |___ CPD |___| 4 13 |___| TCD ___| |___ CPU |___| 5 12 |___| TCU ___| |___ Q2 |___| 6 11 |___| PL ___| |___ Q3 |___| 7 10 |___| P2 ___| |___ GND |___| 8 9 |___| P3 | | |______________| Function Table MR PL CPU CPD Mode H X X X Reset (Asyn.) L L X X Preset (Asyn.) L H H H No Change L H _/ H Count Up L H H _/ Count Down H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial _/ = LOW-to-HIGH Clock Transition Pin Names Description CPU Count Up Clock Input (Active Rising Edge) CPD Count Down Clock Input (Active Rising Edge) MR Asynchronous Master Reset Input (Active H) PL Asynchronous Parallel Load Input (Active LO) P0->P3 Parallel Data Inputs Q0->Q3 Flip-Flop Outputs TCD Terminal CountDown(Borrow)Output(Active LO) TCU Terminal Count Up (Carry) Output (Active LO) General Description The 'F193 is an up/down modulo-16 binary counter. Sepa- rate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-to- HIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Features Y Guaranteed 4000V minimum ESD protection A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will de- crease the count by one. While counting with one clock in- put, the other should be held HIGH, as indicated in the Function Table. The Terminal Count Up (TC U ) and Terminal Count Down (TC D ) outputs are normally HIGH. When the circuit has Function Table MR PL CPU CPD Mode H X X X Reset (Asyn.) L L X X Preset (Asyn.) L H H H No Change L H _/ H Count Up L H H _/ Count Down H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial _/ = LOW-to-HIGH Clock Transition 54F/74F Pin Names Description CPU Count Up Clock Input (Active Rising Edge) CPD Count Down Clock Input (Active Rising Edge) MR Asynchronous Master Reset Input (Active HI) PL Asynchronous Parallel Load Input (Active LO) P0->P3 Parallel Data Inputs Q0->Q3 Flip-Flop Outputs TCD Terminal Count Down(Borrow)Output(Active LO) TCU Terminal Count Up (Carry)Output (Active LOW)