*=============Perfect_LOGIC=======================
Make a sub-circuit and define some limited bandwidth
by using the default mobility and stray C.
*=========The_CMOS_Model_Files==================================
.model NMOSC NMOS(Level= 1 Cbs=2f Cbd=2f)
.model PMOSC PMOS(Level= 1 Cbs=2f Cbd=2f)
*=========Inverter_Real============================================
* ^
* INV_R /_\ VCC
* |
* <-
* ||___
* __|| XINVR A OUT VCC INV
* ___ | ||_ MP1
* |VIN|__| | ___ ^ VCC
* |___| | |__|OUT| /_\
* | _| |___| |\_|
* |__|| ___ | \ __ ___
* ||___ MN1 |A |_| \/ \_|OUT|
* ||-> |___| | /\__/ |___|
* _|_ | /
* /// |/
*
.SUBCKT INVR A OUT VCC
MN1 OUT A 0 0 NMOSC W=1u L=1u
MP1 OUT A VCC VCC PMOSC W=3u L=1u
.ENDS INVR
=======================================================================
And the sub-circuit can be used by adding the following line.
*=========Real_CMOS_SUBCIRCUITS==========================================
*GateNam==IN_A===IN_B===OUT====SUPPLY=SUBCIR_NAME=====================
X_INVR A INVR VCC INVR
=======================================================================
But a behavioral model can also be created and used
by adding the following line.
*=========Behavoural_Logic==========================================
*GateNam==OUTPUT=GND====DEFINE_VOLTAGE===INPUT_A=====INPUT_B==========
B_INVB INVB 0 V = 5 -5*u( u(v(A)-2.5) -.1)
=======================================================================
Depending on what step size is defined for transient analysis,
the behavioral inverter "invb" will appear like a real inverter
"invr" which has infinite bandwidth and gain.
=======================================================================
=======================================================================
At the simple open loop gate level, one would not expect perfect
logic to create any problems.
=======================================================================
CMOS_LOGIC_GATE_Templates
*
* ____ ____ ____
* |\ __| \ __\ \ __\ \ \
* __| \/\__ | \__ | \__ | | \__
* | /\/ __| / ___| / ___| | /
* |/ |___/ /___/ / /___/
*
* __ ____ ____ ____
* | \ __| \ __\ \ __\ \ \
* __|PE\__ | \/\_ | \/\_ | | \/\_
* | / __| /\/ ___| /\/ ___| | /\/
* |_/ |___/ /___/ / /___/
*
=======================================================================
The following shows how some minimum real gates are defined and used.
=======================================================================
VCC VCC 0 DC 5
VA A 0 DC 0 PULSE( 0 5 1p 90p 90p 1n 2n )
VB B 0 DC 0 PULSE( 0 5 1p 90p 90p 3n 6n )
*=========Real_CMOS_SUBCIRCUITS========================================
*GateNam==IN_A===IN_B===OUT====SUPPLY=SUBCIR_NAME=====================
X_INVR A INVR VCC INVR
X_TauR A TAUR VCC TAUR
X_TauB A TAUB VCC TAUB
X_POS_E A VPE VCC POS_E
X_NEG_E A VNE VCC NEG_E
X_AND A B VAND VCC AND
X_NAND A B VNAND VCC NAND
X_OR A B VOR VCC OR
X_NOR A B VNOR VCC NOR
X_XOR A B VXOR VCC XOR
X_XOR2 A B VXOR2 VCC XOR
=======================================================================
The following shows how perfect logic can be defined and used
without the need of any transistor models.
*=========Behavoural_Logic==========================================
*GateNam==OUTPUT=GND====DEFINE_VOLTAGE===INPUT_A=====INPUT_B==========
B_INVB INVB 0 V = 5 -5*u( u(v(A)-2.5) -.1)
B_AND VANDB 0 V = 5*u( u(v(A)-2.5)*u(v(B)-2.5 ) -.1)
B_NAND VNANDB 0 V = 5 -5*u( u(v(A)-2.5)*u(v(B)-2.5 ) -.1)
B_OR VORB 0 V = 5*u( u(v(A)-2.5)+u(v(B)-2.5 ) -.1)
B_NOR VNORB 0 V = 5 -5*u( u(v(A)-2.5)+u(v(B)-2.5 ) -.1)
B_XOR VXORB 0 V 5*u( u(v(A)-2.5)*u(.9-u(v(B)-2.5)) + u(v(B)-2.5)*u(.9-u(v(A)-2.5)) -.1)
The following shows a comparison between real and behavioral models
for a delay element.
=======================================================================
The sub-circuit elements are defined below.
*=========Tau_Real==================================
*
* ___ |\ V1 |\ V2|\ v3|\ V4 |\ V5|\ ___
* |IN |__|1\/\_|2\/\_|3\/\_|1\/\_|2\/\_|3\/\_|OUT|
* |___| | /\/ | /\/ | /\/ | /\/ | /\/ | /\/ |___|
* |/ |/ |/ |/ |/ |/
*
.SUBCKT TAUR A OUT VCC
XINVR1 A V1 VCC INVR
XINVR2 V1 V2 VCC INVR
XINVR3 V2 V3 VCC INVR
XINVR4 V3 V4 VCC INVR
XINVR5 V4 V5 VCC INVR
XINVR6 V5 OUT VCC INVR
.ENDS TAUR
*=========Tau_500p===========================================
* ___
* _/\ /\ /\_____ ____|OUT|
* | \/ \/ | | | |___|
* ___ _|_ RLP _|_ | _|_
* |IN |_/BUF\ ___ |_/OUY\
* |___| \___/ CLP | \___/
* _|_ _|_ _|_
* /// /// ///
*
*
.SUBCKT TAUB IN OUT VCC
BBUF VIN 0 V = 5-5*u( v(IN )-2.5 )
RLP VIN VLP 1K
CLP VLP 0 .5p
BOUT OUT 0 V = 5-5*u( v(VLP )-2.5 )
.ENDS TAUB
=======================================================================
The rising edge and falling edge circuits use the delay with
some added logic.
=======================================================================
*=========POS_Edge============================================
*
* ___ |\ V1 |\ V2|\ V3____ ___
* |A |__|1\/\_|2\/\_|3\/\._| \ ___ ___ | \ ___
* |___|| | /\/ | /\/ | /\/ | 4 \_|OUT| |A |_|PE \_|OUT|
* | |/ |/ |/ _| / |___| |___| | / |___|
* |___________________||___/ |__/
* XPOS_E A VPE VCC POS_E
.SUBCKT POS_E A OUT VCC
XINVR1 A V1 VCC INVR
XINVR2 V1 V2 VCC INVR
XINVR3 V2 V3 VCC INVR
XINVR4 V3 V4 VCC INVR
XINVR5 V4 V5 VCC INVR
XINVR6 V5 V6 VCC INVR
XINVR7 V6 V7 VCC INVR
XAND4 A V7 OUT VCC AND
.ENDS POS_E
*=========NEG_Edge============================================
*
* ___ |\ V1 |\ V2|\ V3____ ___
* |A |__|1\/\_|2\/\_|3\/\._\ \ ___ ___ | \ ___
* |___|| | /\/ | /\/ | /\/ | 4 \/\_|OUT| |A |_|NE \_|OUT|
* | |/ |/ |/ __| /\/ |___| |___| | / |___|
* |___________________|/___/ |__/
* XPOS_E A VPE VCC POS_E
.SUBCKT NEG_E A OUT VCC
XINVR1 A V1 VCC INVR
XINVR2 V1 V2 VCC INVR
XINVR3 V2 V3 VCC INVR
XINVR4 V3 V4 VCC INVR
XINVR5 V4 V5 VCC INVR
XINVR6 V5 V6 VCC INVR
XINVR7 V6 V7 VCC INVR
XNOR4 A V7 OUT VCC NOR
.ENDS NEG_E
=======================================================================
The real and behavior outputs of "AND" and "NAND" are as
follows.
=======================================================================
*=========NAND============================================
* ^ VCC
* /_\
* ________|
* | |
* ___ ||<- ||<- XNAND A B OUT VCC NAND
* |A |____||MP1 _||MP2 ___
* |___| | ||__ | ||_____|OUT| ^ VCC
* | |_/|\____| |___| __ /_\
* | | __| ___ | \_|
* ___ | | || |A |_| \ _ ___
* |B |_/|\_______|_|| MN2 |___| | \/ \_|OUT|
* |___| | ||-> ___ |NAND/\_/ |___|
* | __|V2 |B |_| /
* | || |___| |__/
* |__________|| MN1
* ||->
* _|_
* ///
.SUBCKT NAND A B OUT VCC
MN1 V2 A 0 0 NMOSC W=2u L=1u
MN2 OUT B V2 0 NMOSC W=2u L=1u
MP1 OUT A VCC VCC PMOSC W=3u L=1u
MP2 OUT B VCC VCC PMOSC W=3u L=1u
.ENDS NAND
*=========AND============================================
* ^ ^
* /_\ /_\
* ________|VCC | VCC
* | | ||<-
* ___ ||<- ||<- __||MP3 XAND A B OUT VCC AND
* |A |____||MP1 _||MP2 | ||__
* |___| | ||__ | ||_____| | ^ VCC
* | |_/|\____| |VG | ___ __ /_\
* | | __| | |__|OUT| ___ | \_|
* ___ | | || | | |___| |A |_| \ ___
* |B |_/|\_______|_|| MN2 | | |___| | \_|OUT|
* |___| | ||-> | | ___ |AND / |___|
* | __|V2| __| |B |_| /
* | || | || |___| |__/
* |__________|| MN1 |_|| MN3
* ||-> ||->
* _|_ _|_
* /// ///
.SUBCKT AND A B OUT VCC
MN1 V2 A 0 0 NMOSC W=2u L=1u
MN2 VG B V2 0 NMOSC W=2u L=1u
MN3 OUT VG 0 0 NMOSC W=2u L=1u
MP1 VG A VCC VCC PMOSC W=3u L=1u
MP2 VG B VCC VCC PMOSC W=3u L=1u
MP3 OUT VG VCC VCC PMOSC W=3u L=1u
.ENDS AND
*=========AND_NAND_Perfect_Logic============================================
B_AND VANDB 0 V = 5*u( u(v(A)-2.5)*u(v(B)-2.5 ) -.1)
B_NAND VNANDB 0 V = 5 -5*u( u(v(A)-2.5)*u(v(B)-2.5 ) -.1)
=======================================================================
The real and behavior outputs of "OR" and "NOR" are as
follows.
=======================================================================
*=========NOR============================================
* ^
* /_\ VCC
* |
* ||<- XNOR A B OUT VCC NOR
* __________||MP1
* | ||__ ^ VCC
* | | V2 ___ /_\
* ___ | ||<- ___ \ \_|
* |A |_/|\_________||MP2 ___ |A |__\ \ _ ___
* |___| | | ||_____|OUT| |___| | \/ \_|OUT|
* | | | |___| ___ |NOR /\_/ |___|
* | __/|\____| |B |__/ /
* | __| | __| |___| /___/
* ___ | || | ||
* |B |__|_|| MN1 |_|| MN2
* |___| ||-> ||->
* _|_ _|_
* /// ///
.SUBCKT NOR A B OUT VCC
MN1 OUT B 0 0 NMOSC W=1u L=1u
MN2 OUT A 0 0 NMOSC W=1u L=1u
MP1 V2 B VCC VCC PMOSC W=3u L=1u
MP2 OUT A V2 VCC PMOSC W=3u L=1u
.ENDS NOR
*=========OR============================================
* ^ ^
* /_\ /_\
* | | VCC
* ||<- ||<- XOR A B OUT VCC OR
* __________||MP1 __||MP3
* | ||__ | ||__ ^ VCC
* | |V2| | ___ /_\
* ___ | ||<- | | ___ ___ \ \_|
* |A |_/|\_________||MP2 | |__|OUT| |A |__\ \ ___
* |___| | | ||_____|VG | |___| |___| | \_|OUT|
* | | | | | ___ |OR2 / |___|
* | __/|\____| | | |B |__/ /
* | __| | __| | __| |___| /___/
* ___ | || | || | ||
* |B |__|_|| MN1 |_|| MN2 |_|| MN3
* |___| ||-> ||-> ||->
* _|_ _|_ _|_
* /// /// ///
.SUBCKT OR A B OUT VCC
MN1 VG A 0 0 NMOSC W=1u L=1u
MN2 VG B 0 0 NMOSC W=1u L=1u
MN3 OUT VG 0 0 NMOSC W=1u L=1u
MP1 V2 B VCC VCC PMOSC W=6u L=1u
MP2 VG A V2 VCC PMOSC W=6u L=1u
MP3 OUT VG VCC VCC PMOSC W=3u L=1u
.ENDS OR
*=========OR_NOR_Perfect_Logic============================================
B_OR VORB 0 V = 5*u( u(v(A)-2.5)+u(v(B)-2.5 ) -.1)
B_NOR VNORB 0 V = 5 -5*u( u(v(A)-2.5)+u(v(B)-2.5 ) -.1)
=======================================================================
But for "XOR" gates, the difference between real and behavior outputs
becomes apparent. Two different real versions using CMOS transistors are
shown. The output of "vxor" is done using transistors. The output of
"vxor2" is done using gate sub-circuits. Notice that in both cases, that
there are some timing delays for all the gate voltages to get up to
their steady state. The behavioral logic output "vxorb" has no time delays.
=======================================================================
*=========XOR============================================
* ^ VCC ^
* /_\ /_\
* | |
* ||<- ||<-
* ^ VCC ^ NB_||MP3 NA_||MP5
* /_\ /_\ ||__ ||__
* | | |_________| XAB
* ||<- ||<- | |
* __||MP1 __||MP2 ||<- ||<-
* | ||__ | ||__ A_||MP4 B_||MP6 ___
* | | | | ||__ ||_____|OUT| XXOR A B OUT VCC XOR
* | | | | |_________| |___|
* | |-> | |-> __| __| ^ VCC
* | |NA | |NB || || ____ /_\
* | | | | NA_|| MN3 A_|| MN5 ___ \ \ \_|
* | | | | ||-> ||-> |A |__\ \ \ ___
* | __| | __| __|NAB __|AB |___| | | \_|OUT|
* ___ | || ___ | || || || ___ | |XOR / |___|
* |A |_|_|| MN1 |B |_|_|| MN2 NB_|| MN4 B_|| MN6 |B |__/ / /
* |___| ||-> |___| ||-> ||-> ||-> |___| / / __/
* _|_ _|_ _|_ _|_
* /// /// /// ///
*
.SUBCKT XOR A B OUT VCC
MN1 NA A 0 0 NMOSC W=1u L=1u
MN2 NB B 0 0 NMOSC W=1u L=1u
MN3 OUT NA NAB 0 NMOSC W=2u L=1u
MN4 NAB NB 0 0 NMOSC W=2u L=1u
MN5 OUT A AB 0 NMOSC W=2u L=1u
MN6 AB B 0 0 NMOSC W=2u L=1u
MP1 NA A VCC VCC PMOSC W=3u L=1u
MP2 NB B VCC VCC PMOSC W=3u L=1u
MP3 XAB NB VCC VCC PMOSC W=3u L=1u
MP4 OUT A XAB VCC PMOSC W=3u L=1u
MP5 XAB NA VCC VCC PMOSC W=3u L=1u
MP6 OUT B XAB VCC PMOSC W=3u L=1u
.ENDS XOR
*=========XOR2============================================
* ___ ____
* |A |_____________| \ NAAB ^ VCC
* |___| | \/\_ ____ ____ /_\
* | ____ NAB__| /\/ |__| \ ___ ___ \ \ \_|
* |___| \ | |___/ | \/\_|OUT| |A |__\ \ \ ___
* |NAND\/\_| ____ __| /\/ |___| |___| | | \_|OUT|
* ___| /\/ |__| \ | |___/ ___ | |XOR / |___|
* _|_ |___/ | \/\_| |B |__/ / /
* |B |_____________| /\/ NBAB |___| / / __/
* |___| |___/
*
.SUBCKT XOR2 A B OUT VCC
XNAND1 A B NAB VCC NAND
XNAND2 A NAB NAAB VCC NAND
XNAND3 B NAB NBAB VCC NAND
XNAND4 NAAB NBAB OUT VCC NAND
.ENDS XOR2
.end
*=========XOR_Perfect_Logic============================================
B_XOR VXORB 0 V 5*u( u(v(A)-2.5)*u(.9-u(v(B)-2.5)) + u(v(B)-2.5)*u(.9-u(v(A)-2.5)) -.1)
=======================================================================
These time delay effects on gate voltages restate an assumption
requirement in the digital world.
"All inputs must settle to a stationary state to have a correct output."
=======================================================================
When logic is used in an open loop fashion, the time delays
means that one might want to wait for an output to become
valid. But binary counters often use Flip Flops where an
output is fed back to an input. In this case, the time delays
are actually a requirement for convergence.
===========Full_Netlist_For_Copy_Paste=======================
CMOS_LOGIC_GATE_Templates
*
* ____ ____ ____
* |\ __| \ __\ \ __\ \ \
* __| \/\__ | \__ | \__ | | \__
* | /\/ __| / ___| / ___| | /
* |/ |___/ /___/ / /___/
*
* __ ____ ____ ____
* | \ __| \ __\ \ __\ \ \
* __|PE\__ | \/\_ | \/\_ | | \/\_
* | / __| /\/ ___| /\/ ___| | /\/
* |_/ |___/ /___/ / /___/
*
.OPTIONS GMIN=1e-18 METHOD=traps
*======== ====== ====== ====== ====== ====== ====== ====== ====== ======
VCC VCC 0 DC 5
VA A 0 DC 0 PULSE( 0 5 1p 90p 90p 1n 2n )
VB B 0 DC 0 PULSE( 0 5 1p 90p 90p 3n 6n )
X_INVR A INVR VCC INVR
X_TauR A TAUR VCC TAUR
X_TauB A TAUB VCC TAUB
X_POS_E A VPE VCC POS_E
X_NEG_E A VNE VCC NEG_E
X_AND A B VAND VCC AND
X_NAND A B VNAND VCC NAND
X_OR A B VOR VCC OR
X_NOR A B VNOR VCC NOR
X_XOR A B VXOR VCC XOR
X_XOR2 A B VXOR2 VCC XOR
B_INVB INVB 0 V = 5 -5*u( u(v(A)-2.5) -.1)
B_AND VANDB 0 V = 5*u( u(v(A)-2.5)*u(v(B)-2.5 ) -.1)
B_NAND VNANDB 0 V = 5 -5*u( u(v(A)-2.5)*u(v(B)-2.5 ) -.1)
B_OR VORB 0 V = 5*u( u(v(A)-2.5)+u(v(B)-2.5 ) -.1)
B_NOR VNORB 0 V = 5 -5*u( u(v(A)-2.5)+u(v(B)-2.5 ) -.1)
B_XOR VXORB 0 V 5*u( u(v(A)-2.5)*u(.9-u(v(B)-2.5)) + u(v(B)-2.5)*u(.9-u(v(A)-2.5)) -.1)
*XAND3 A B VAND VAND3 VCC AND3
*XNAND3 A B VAND VNAND3 VCC NAND3
*======== ====== ====== ====== ====== ====== ====== ====== ====== ======
*TRAN TSTEP TSTOP TSTART TMAX ?UIC?
.tran 1p 10n 0 1p UIC
*=========Run_Sim============================================
.control
run
set pensize = 2
plot a invr-10 invb-20
plot a taur -3 tauB -6
plot a vpe-10 vne-20
plot a b-10 vand-20 vnand-30 vandb-40 vnandb-50
plot a b-10 vor-20 vnor-30 vorb-40 vnorb-50
plot a b-10 vxor-20 vxor2-30 vxorb-40
.endc
*=========The_CMOS_Model_Files==================================
.model NMOSC NMOS(Level= 1 Cbs=2f Cbd=2f)
.model PMOSC PMOS(Level= 1 Cbs=2f Cbd=2f)
*=========Inverter_Real============================================
* ^
* INV_R /_\ VCC
* |
* <-
* ||___
* __|| XINVR A OUT VCC INV
* ___ | ||_ MP1
* |VIN|__| | ___ ^ VCC
* |___| | |__|OUT| /_\
* | _| |___| |\_|
* |__|| ___ | \ __ ___
* ||___ MN1 |A |_| \/ \_|OUT|
* ||-> |___| | /\__/ |___|
* _|_ | /
* /// |/
*
.SUBCKT INVR A OUT VCC
MN1 OUT A 0 0 NMOSC W=1u L=1u
MP1 OUT A VCC VCC PMOSC W=3u L=1u
.ENDS INVR
*=========Tau_Real==================================
*
* ___ |\ V1 |\ V2|\ v3|\ V4 |\ V5|\ ___
* |IN |__|1\/\_|2\/\_|3\/\_|1\/\_|2\/\_|3\/\_|OUT|
* |___| | /\/ | /\/ | /\/ | /\/ | /\/ | /\/ |___|
* |/ |/ |/ |/ |/ |/
*
.SUBCKT TAUR A OUT VCC
XINVR1 A V1 VCC INVR
XINVR2 V1 V2 VCC INVR
XINVR3 V2 V3 VCC INVR
XINVR4 V3 V4 VCC INVR
XINVR5 V4 V5 VCC INVR
XINVR6 V5 OUT VCC INVR
.ENDS TAUR
*=========Tau_500p===========================================
* ___
* _/\ /\ /\_____ ____|OUT|
* | \/ \/ | | | |___|
* ___ _|_ RLP _|_ | _|_
* |IN |_/BUF\ ___ |_/OUY\
* |___| \___/ CLP | \___/
* _|_ _|_ _|_
* /// /// ///
*
*
.SUBCKT TAUB IN OUT VCC
BBUF VIN 0 V = 5-5*u( v(IN )-2.5 )
RLP VIN VLP 1K
CLP VLP 0 .5p
BOUT OUT 0 V = 5-5*u( v(VLP )-2.5 )
.ENDS TAUB
*=========POS_Edge============================================
*
* ___ |\ V1 |\ V2|\ V3____ ___
* |A |__|1\/\_|2\/\_|3\/\._| \ ___ __ | \ ___
* |___|| | /\/ | /\/ | /\/ | 4 \_|OUT| |A |_|PE \_|OUT|
* | |/ |/ |/ _| / |___| |___| | / |___|
* |___________________||___/ |__/
* XPOS_E A VPE VCC POS_E
.SUBCKT POS_E A OUT VCC
XINVR1 A V1 VCC INVR
XINVR2 V1 V2 VCC INVR
XINVR3 V2 V3 VCC INVR
XINVR4 V3 V4 VCC INVR
XINVR5 V4 V5 VCC INVR
XINVR6 V5 V6 VCC INVR
XINVR7 V6 V7 VCC INVR
XAND4 A V7 OUT VCC AND
.ENDS POS_E
*=========NEG_Edge============================================
*
* ___ |\ V1 |\ V2|\ V3____ ___
* |A |__|1\/\_|2\/\_|3\/\._\ \ ___ __ | \ ___
* |___|| | /\/ | /\/ | /\/ | 4 \/\_|OUT| |A |_|NE \_|OUT|
* | |/ |/ |/ __| /\/ |___| |___| | / |___|
* |___________________|/___/ |__/
* XPOS_E A VPE VCC POS_E
.SUBCKT NEG_E A OUT VCC
XINVR1 A V1 VCC INVR
XINVR2 V1 V2 VCC INVR
XINVR3 V2 V3 VCC INVR
XINVR4 V3 V4 VCC INVR
XINVR5 V4 V5 VCC INVR
XINVR6 V5 V6 VCC INVR
XINVR7 V6 V7 VCC INVR
XNOR4 A V7 OUT VCC NOR
.ENDS NEG_E
*=========NAND============================================
* ^ VCC
* /_\
* ________|
* | |
* ___ ||<- ||<- XNAND A B OUT VCC NAND
* |A |____||MP1 _||MP2 ___
* |___| | ||__ | ||_____|OUT| ^ VCC
* | |_/|\____| |___| __ /_\
* | | __| ___ | \_|
* ___ | | || |A |_| \ _ ___
* |B |_/|\_______|_|| MN2 |___| | \/ \_|OUT|
* |___| | ||-> ___ |NAND/\_/ |___|
* | __|V2 |B |_| /
* | || |___| |__/
* |__________|| MN1
* ||->
* _|_
* ///
.SUBCKT NAND A B OUT VCC
MN1 V2 A 0 0 NMOSC W=2u L=1u
MN2 OUT B V2 0 NMOSC W=2u L=1u
MP1 OUT A VCC VCC PMOSC W=3u L=1u
MP2 OUT B VCC VCC PMOSC W=3u L=1u
.ENDS NAND
*=========AND============================================
* ^ ^
* /_\ /_\
* ________|VCC | VCC
* | | ||<-
* ___ ||<- ||<- __||MP3 XAND A B OUT VCC AND
* |A |____||MP1 _||MP2 | ||__
* |___| | ||__ | ||_____| | ^ VCC
* | |_/|\____| |VG | ___ __ /_\
* | | __| | |__|OUT| ___ | \_|
* ___ | | || | | |___| |A |_| \ ___
* |B |_/|\_______|_|| MN2 | | |___| | \_|OUT|
* |___| | ||-> | | ___ |AND / |___|
* | __|V2| __| |B |_| /
* | || | || |___| |__/
* |__________|| MN1 |_|| MN3
* ||-> ||->
* _|_ _|_
* /// ///
.SUBCKT AND A B OUT VCC
MN1 V2 A 0 0 NMOSC W=2u L=1u
MN2 VG B V2 0 NMOSC W=2u L=1u
MN3 OUT VG 0 0 NMOSC W=2u L=1u
MP1 VG A VCC VCC PMOSC W=3u L=1u
MP2 VG B VCC VCC PMOSC W=3u L=1u
MP3 OUT VG VCC VCC PMOSC W=3u L=1u
.ENDS AND
*=========NAND3============================================
*
* ^ VCC
* /_\
* _________________|
* | | |
* ___ ||<- ||<- ||<-
* |A |____||MP1 _||MP2 _||MP3 ___
* |___| | ||__ | ||__ | ||______|OUT|
* | |_/|\____|_/|\____| |___|
* | | | |
* | | | __|
* ___ | | | ||
* |B |_/|\______/|\_______|_|| MN3 XNAND3 A B C OUT VCC NAND3
* |___| | | ||->
* | | __|V3 ___ ^ VCC
* ___ | | || |A |____ /_\
* |C |_/|\_______|__________|| MN2 |___| | \_|
* |___| | ||-> ___ | \ ___
* | __|V2 |B |_| \/\_|OUT|
* | || |___| |AND /\/ |___|
* |___________________|| MN1 ___ | /
* ||-> |C |_|__/
* _|_ |___|
* ///
*
.SUBCKT NAND3 A B C OUT VCC
MN1 V2 A 0 0 NMOSC W=3u L=1u
MN2 V3 B V2 0 NMOSC W=3u L=1u
MN3 OUT C V3 0 NMOSC W=3u L=1u
MP1 OUT A VCC VCC PMOSC W=3u L=1u
MP2 OUT B VCC VCC PMOSC W=3u L=1u
MP3 OUT C VCC VCC PMOSC W=3u L=1u
.ENDS NAND3
*=========AND3============================================
*
* ^ VCC ^
* /_\ /_\
* _________________| | VCC
* | | | ||<-
* ___ ||<- ||<- ||<- __||MP4
* |A |____||MP1 _||MP2 _||MP3 | ||__
* |___| | ||__ | ||__ | ||_____| |
* | |_/|\____|_/|\____| |VG | ___
* | | | | | |__|OUT|
* | | | __| | | |___|
* ___ | | | || | |
* |B |_/|\______/|\_______|_|| MN3 | | XAND3 A B C OUT VCC AND3
* |___| | | ||-> | |
* | | __|V3| | ___ ^ VCC
* ___ | | || | | |A |____ /_\
* |C |_/|\_______|__________|| MN2 | | |___| | \_|
* |___| | ||-> | | ___ | \ ___
* | __|V2| __| |B |_| \_|OUT|
* | || | || |___| |AND / |___|
* |___________________|| MN1 |_|| MN4 ___ | /
* ||-> ||-> |C |_|__/
* _|_ _|_ |___|
* /// ///
*
.SUBCKT AND3 A B C OUT VCC
MN1 V2 A 0 0 NMOSC W=3u L=1u
MN2 V3 B V2 0 NMOSC W=3u L=1u
MN3 VG C V3 0 NMOSC W=3u L=1u
MN4 OUT VG 0 0 NMOSC W=1u L=1u
MP1 VG A VCC VCC PMOSC W=3u L=1u
MP2 VG B VCC VCC PMOSC W=3u L=1u
MP3 VG C VCC VCC PMOSC W=3u L=1u
MP4 OUT VG VCC VCC PMOSC W=3u L=1u
.ENDS AND3
*=========NOR============================================
* ^
* /_\ VCC
* |
* ||<- XNOR A B OUT VCC NOR
* __________||MP1
* | ||__ ^ VCC
* | | V2 ___ /_\
* ___ | ||<- ___ \ \_|
* |A |_/|\_________||MP2 ___ |A |__\ \ _ ___
* |___| | | ||_____|OUT| |___| | \/ \_|OUT|
* | | | |___| ___ |NOR /\_/ |___|
* | __/|\____| |B |__/ /
* | __| | __| |___| /___/
* ___ | || | ||
* |B |__|_|| MN1 |_|| MN2
* |___| ||-> ||->
* _|_ _|_
* /// ///
.SUBCKT NOR A B OUT VCC
MN1 OUT B 0 0 NMOSC W=1u L=1u
MN2 OUT A 0 0 NMOSC W=1u L=1u
MP1 V2 B VCC VCC PMOSC W=3u L=1u
MP2 OUT A V2 VCC PMOSC W=3u L=1u
.ENDS NOR
*=========OR============================================
* ^ ^
* /_\ /_\
* | | VCC
* ||<- ||<- XOR A B OUT VCC OR
* __________||MP1 __||MP3
* | ||__ | ||__ ^ VCC
* | |V2| | ___ /_\
* ___ | ||<- | | ___ ___ \ \_|
* |A |_/|\_________||MP2 | |__|OUT| |A |__\ \ ___
* |___| | | ||_____|VG | |___| |___| | \_|OUT|
* | | | | | ___ |OR2 / |___|
* | __/|\____| | | |B |__/ /
* | __| | __| | __| |___| /___/
* ___ | || | || | ||
* |B |__|_|| MN1 |_|| MN2 |_|| MN3
* |___| ||-> ||-> ||->
* _|_ _|_ _|_
* /// /// ///
.SUBCKT OR A B OUT VCC
MN1 VG A 0 0 NMOSC W=1u L=1u
MN2 VG B 0 0 NMOSC W=1u L=1u
MN3 OUT VG 0 0 NMOSC W=1u L=1u
MP1 V2 B VCC VCC PMOSC W=6u L=1u
MP2 VG A V2 VCC PMOSC W=6u L=1u
MP3 OUT VG VCC VCC PMOSC W=3u L=1u
.ENDS OR
*=========XOR============================================
* ^ VCC ^
* /_\ /_\
* | |
* ||<- ||<-
* ^ VCC ^ NB_||MP3 NA_||MP5
* /_\ /_\ ||__ ||__
* | | |_________| XAB
* ||<- ||<- | |
* __||MP1 __||MP2 ||<- ||<-
* | ||__ | ||__ A_||MP4 B_||MP6 ___
* | | | | ||__ ||_____|OUT| XXOR A B OUT VCC XOR
* | | | | |_________| |___|
* | |-> | |-> __| __| ^ VCC
* | |NA | |NB || || ____ /_\
* | | | | NA_|| MN3 A_|| MN5 ___ \ \ \_|
* | | | | ||-> ||-> |A |__\ \ \ ___
* | __| | __| __|NAB __|AB |___| | | \_|OUT|
* ___ | || ___ | || || || ___ | |XOR / |___|
* |A |_|_|| MN1 |B |_|_|| MN2 NB_|| MN4 B_|| MN6 |B |__/ / /
* |___| ||-> |___| ||-> ||-> ||-> |___| / / __/
* _|_ _|_ _|_ _|_
* /// /// /// ///
*
.SUBCKT XOR A B OUT VCC
MN1 NA A 0 0 NMOSC W=1u L=1u
MN2 NB B 0 0 NMOSC W=1u L=1u
MN3 OUT NA NAB 0 NMOSC W=2u L=1u
MN4 NAB NB 0 0 NMOSC W=2u L=1u
MN5 OUT A AB 0 NMOSC W=2u L=1u
MN6 AB B 0 0 NMOSC W=2u L=1u
MP1 NA A VCC VCC PMOSC W=3u L=1u
MP2 NB B VCC VCC PMOSC W=3u L=1u
MP3 XAB NB VCC VCC PMOSC W=3u L=1u
MP4 OUT A XAB VCC PMOSC W=3u L=1u
MP5 XAB NA VCC VCC PMOSC W=3u L=1u
MP6 OUT B XAB VCC PMOSC W=3u L=1u
.ENDS XOR
*=========XOR2============================================
* ___ ____
* |A |_____________| \ NAAB ^ VCC
* |___| | \/\_ ____ ____ /_\
* | ____ NAB__| /\/ |__| \ ___ ___ \ \ \_|
* |___| \ | |___/ | \/\_|OUT| |A |__\ \ \ ___
* |NAND\/\_| ____ __| /\/ |___| |___| | | \_|OUT|
* ___| /\/ |__| \ | |___/ ___ | |XOR / |___|
* _|_ |___/ | \/\_| |B |__/ / /
* |B |_____________| /\/ NBAB |___| / / __/
* |___| |___/
*
.SUBCKT XOR2 A B OUT VCC
XNAND1 A B NAB VCC NAND
XNAND2 A NAB NAAB VCC NAND
XNAND3 B NAB NBAB VCC NAND
XNAND4 NAAB NBAB OUT VCC NAND
.ENDS XOR2
.end