A MORE ACCURATE LM13700 SPICE SUBCIRCUIT
The on-line spice models for the LM13600/LM13700 are bare-bone in that the transistor
models usually leave out some important parameters. The following are the important
parameters which are needed.
First off, the Bandwidth for the LM13600/LM13700 is defined by the lateral PNPs and
both capacitance and TF need to be adjusted to match silicon. This will effect high
frequency performance.
Second, the lateral PNPs are operating in high level ejection. In others words, the
VBE of a lateral PNP can be twice that of an NPN. This will effect low supply
voltage performance.
Third, processing defines how well beta holds up over emitter current. In the LM13600
application, this defines the dynamic range for something like a function generator.
First silicon for the LM13600 could make a triangle/square wave VCO which could go from
500KHz down to a few Hertz. If the present process for the LM13700 has tracked the
industry, then the new dynamic range might go from 500kHz to the milli Hertz range.
A full working LM13700 sub-circuit using best guess
transistor models can be found by
saving the linked file from here. To make things easy, the
sub-circuit is pinouted to
match the IC pinout.
* ==============The_SubCircuit=====================================
*
* LIN INP INN IAB OUT VCC BIN BUF
* __|____|____|____|____|____|____|____|__
* | | | |_|\ |__ |__ ____| | |
* | | | |-\ _| _ | | -> |
* | |___/|\_____| \/ \/ \_| | ->_|' |
* | | -> | /\_/\_/ |_|' |`_ |
* | |______|+/ |`______| |
* | |/ | |
* | HALF13700 |
* |________________________________________|
*
* The pinout matches the LM13700
.SUBCKT HALF13700 LIN INP INN IAB OUT VCC BIN BUF
QN1 IAB VN2B 0 npnv 3
QN2 VN2B VN2B 0 npnv 3
QN3 VN3C IAB VN2B npnv 3
QN4 VP3B INN VN3C npnv 3
QN5 VP6B INP VN3C npnv 3
QN6 LIN LIN INN npnv 3
QN7 LIN LIN INP npnv 3
QN8 VN10B VN9B 0 npnv 3
QN9 VN9B VN9B 0 npnv 3
QN10 OUT VN10B VN9B npnv 3
QN11 VCC BIN VN12B npnv 15
QN12 VN12B VN12B BUF npnv 3
QN13 VCC VN12B BUF npnv 150
QP1 VP3B VP2B VCC pnpl 3
QP2 VP2B VP2B VCC pnpl 3
QP3 VN10B VP3B VP2B pnpl 3
QP4 VP6B VP5B VCC pnpl 3
QP5 VP5B VP5B VCC pnpl 3
QP6 OUT VP6B VP5B pnpl 3
.ends
* ^ VCC
* /_\
* _____|____________________________________________
* | | | | | |
* -> <- -> <- ___ _| |
* QP1 `|___|' QP2 QP4 `|___|'QP5 |BIN|_|' QN11 |
* _ '| | |`_ _ '| | |`_ |___| |`-> _|
* ___ | |____| | |____| VN12B |___|'QN13
* |LIN| | VP2B | | VP5B | ____| |`->
* |___| | <- | <- | _| |
* QN6 | |______|'QP3 |______|'QP6 |_|' QN12 |
* _________|_ |VP3B |`_ |VP6B |`_ |`-> |
* | _| | _| | | ______| | |______|
* |_|' |_|' QN7 | | | | |
* |`-> |`-> | |_/|\_____ | _|_
* | | | | | | |BUF|
* ___ | | _| |_ | | ___ |___|
* |INN|_|_____/|\__|' QN4 QN5 `|_ | |_|OUT|
* |___| | |`-> <-'| | | | |___|
* | |____________| | | |
* ___ | VN3C | | | |
* |INP|________|__________________/|\___| | |
* |___| | | |
* ___ _| |VN10B _|
* |IBA|___________|' QN3 |______|'QN10
* |___| | |`-> | |`->
* | VN2B____| | VN9B____|
* |_ | _| |_ | _|
* QN1 `|_|_|' QN2 QN8 `|_|_|' QN9
* <-'| |`-> <-'| |`->
* | | | |
* |_________|______|_________|
* _|_
* ///
*
* The output can only swing to within a diode and a sat of the rails.
* Input common mode range is 2 diodes from bottom and 1 diode from top.
*
Effort needs to be put in the models to address what happens at low supply voltages.
The LM13700 was design for a +/- 15volt supply. It can work in a 5volt supply application
provided one understands both the input and output voltage swing limitations. In particular,
the high VBE voltage for the lateral PNPs needs to be watched out for.
The following models define both speed and DC voltage parameters for the sub-circuit.
These model represent how first silicon for the LM13600 used to work.
* ==============The_Standard_Bipolar_Models==========================
.MODEL npnv NPN(
*==========================================================
+IS=1.1E-18 NF=1.005 BF=220 VAF=130 IKF=5e-03
+ISE=9.15E-15 NE=2
*==========================================================
+CJE=2E-12 CJC=2E-13 CJS=3E-12 TF=.6E-9 )
.MODEL pnpl PNP(
*==========================================================
+IS=1.1E-18 NF=1.8 BF=5 VAF=170 IKF=6e-03
+ISE=3E-15 NE=3
*==========================================================
+CJE=4E-12 CJC=6E-13 CJS=5E-12 TF=70E-9 )
* The models are a best guess as to the old standard process
The following application of the sub-circuit shows half of a LM13700 being bias up
on a 10 volt supply. This is more of a functionality check in terms of low supply
operation and bandwidth performance.
* ===============SUBCIRCUIT_10V_APPLICATION============================
LM13700_SUB
*
*
* ^ VCC
* /_\ R1 1K R2 1K
* |
* |_/\ /\ /\___/\ /\ /\_
* \/ \/ | \/ \/ _|_
* | ///
* | ^
* ^ VCC | /_\ VCC
* /_\ _______| | R3 1K R4 1k
* | | | ____|_/\ /\ /\___/\ /\ /\_
* _|_ | | _|_ \/ \/ | \/ \/ _|_
* /VCC\ _|_ | / _ \ __| ///
* \___/ /VIN\ | \/ \/ 1ma |
* _|_ \___/ | /\_/\IBias | __/\ /\ /\_
* /// | | \___/ _________| | \/ \/ _|_
* | | | | | | ///
* LIN INP INN IAB OUT VCC BIN BUF R6 1Meg
* __|____|____|____|____|____|____|____|__
* | | | |_|\ |__ |__ ____| | |
* | | | |-\ _| _ | | -> |
* | |___/|\_____| \/ \/ \_| | ->_|' |
* | | -> | /\_/\_/ |_|' |`_ |
* | |______|+/ |`______| |
* | |/ | |
* | HALF13700 |
* |________________________________________|
*
*
* The subcircuit gets dc biased up at 10V to run AC
.OPTIONS GMIN =1e-18 METHOD =TRAP set srcsteps = 1
VCC VCC 0 DC 10
VIN INP INN SIN( 0 100m 1k ) AC 1m
IBias VCC IAB 1m
R1 VCC INN 1k
R2 INN 0 1k
R3 VCC OUT 1k
R4 OUT 0 1k
XOTA LIN INP INN IAB OUT VCC BIN BUF HALF13700
R5 BIN OUT 1
R6 BUF 0 1000k
.control
set pensize = 2
tran 1u 10m
run
plot v(inp) v(inn) v(out)
ac dec 200 1 10000k
plot db(v(out))
.endc
* Both AC and Transient waveforms are produced.
* A large input will distort the output.
* The Bandwidth is set by the PNPL at 2MHz.
The LM13700 behavior is completely defined by its transistor models. Ideally,
the parameters of the transistor models should get adjusted to match silicon.
The NPN does not dominate the bandwidth of the LM13700. But this is what standard
NPNs used to do in terms of bandwidth.
* ===============NPN_Model_ft_Calibration============================
* A MacSpice example on how to do Ft can be found here.
.MODEL NPNV NPN(
*==========================================================
+IS=1.1E-17 BF=120 VAF=30 IKF=1e-03
*==========================================================
+CJE=2E-12
+CJC=2E-13
+CJS=3E-12
+TF=.6E-9 )
* The capacitance and TF value are adjusted to match silicon.
The lateral pnps had some real speed limitations. These transistor were barely working
in that their beta was around 5 and they were at least 100 times slower than the NPNs.
At high emitter currents, the transient time across the base (which was large) limited
their ft to around 2MHz. At low emitter currents, stray capacitance dominated the speed
of the lateral PNPs.
* ===============PNPL_Model_ft_Calibration============================
* A MacSpice example on how to do Ft can be found here.
.MODEL pnpl PNP(
*==========================================================
+IS=1.1E-18 NF=1.8 BF=5 VAF=170 IKF=6e-03
+ISE=3E-15 NE=3
*==========================================================
+CJE=4E-12 CJC=6E-13 CJS=5E-12 TF=70E-9 )
* The capacitance and TF value are adjusted to match silicon.
The NPNs behaved more or less like this in terms of Beta for first silicon.
* ===============NPN_Model_VBE_Calibration============================
NPN_gummel
*
* ________
* | | VC
* |C _|_
* B _| /2v \
* ____|' npnv \___/
* | |`-> |
* VB _|_ | 0 |
* /.7v\ |________|
* \___/ _|_
* | ///
* _|_
* ///
VC C 0 DC 5V
VB B 0 0V
Q1 C B 0 NPNV
.MODEL NPNV NPN(
*==========================================================
+IS=1.1E-18 NF=1.005 BF=220 VAF=130 IKF=5e-03
+ISE=9.15E-15 NE=2
*==========================================================
+CJE=2E-12 CJC=2E-13 CJS=3E-12 TF=.6E-9 )
.OPTIONS GMIN=1e-15 METHOD=gear ABSTOL=1e-15
.control
dc vb .4V 1.2V .1V
plot mag(-i(vc)) mag(-i(vb)) vs mag(V(b)) ylog title Gummel
plot mag(i(vc)/i(vb)) vs mag(vc#branch) loglog title Beta_vs_IC
.endc
.end
* The Model terms define beta over emitter current.
The lateral PNPs however had VBE voltages almost double that of the NPNs.
The value for NF was chosen to match silicon of that time.
* ===============PNPL_Model_VBE_Calibration============================
LPNP_gummel_CLIC
*
* ________
* | | VC
* |C _|_
* B _| /-2v\
* ____|' pnpl \___/
* | |`<- |
* VB _|_ | 0 |
* /0v \ |________|
* \___/ _|_
* | ///
* _|_
* ///
VC C 0 DC -5V
VB B 0 0V
Q1 C B 0 PNPL
.MODEL pnpl PNP(
*==========================================================
+IS=1.1E-18 NF=1.8 BF=5 VAF=170 IKF=6e-03
+ISE=3E-15 NE=3
*==========================================================
+CJE=4E-12 CJC=6E-13 CJS=5E-12 TF=70E-9 )
.OPTIONS GMIN=1e-15 METHOD=gear ABSTOL=1e-15
.control
dc vb -.9V -1.9V -.1V
plot mag(-i(vc)) mag(-i(vb)) vs mag(V(b)) ylog title Gummel
plot mag(i(vc)/i(vb)) vs mag(vc#branch) loglog title Beta_vs_IC
.endc
.end
*
Old PNPL were in high level ejection NF=1.8
* The Vbe for PNPL can be twice that of NPNs.
On a 10volt supply application, the large VBEs of the lateral PNPs is not
so critical. In a 5 volt application, running a Iabc current of 1mA may be
high enough to start effecting the input common mode voltage and the output
swing.
* ===============SUBCIRCUIT_10V_APPLICATION============================
LM13700_SUB
*
* ^ VCC
* /_\ R1 1K R2 1K
* |
* |_/\ /\ /\___/\ /\ /\_
* \/ \/ | \/ \/ _|_
* | ///
* | ^
* ^ VCC | /_\ VCC
* /_\ _______| | R3 1K R4 1k
* | | | ____|_/\ /\ /\___/\ /\ /\_
* _|_ | | _|_ \/ \/ | \/ \/ _|_
* /VCC\ _|_ | / _ \ __| ///
* \___/ /VIN\ | \/ \/ 1ma |
* _|_ \___/ | /\_/\IBias | __/\ /\ /\_
* /// | | \___/ _________| | \/ \/ _|_
* | | | | | | ///
* LIN INP INN IAB OUT VCC BIN BUF R6 1Meg
* __|____|____|____|____|____|____|____|__
* | | | |_|\ |__ |__ ____| | |
* | | | |-\ _| _ | | -> |
* | |___/|\_____| \/ \/ \_| | ->_|' |
* | | -> | /\_/\_/ |_|' |`_ |
* | |______|+/ |`______| |
* | |/ | |
* | HALF13700 |
* |________________________________________|
*
*
* Biasing the subcircuit at 5V affects the AC outout swing.
.OPTIONS GMIN =1e-18 METHOD =TRAP set srcsteps = 1
VCC VCC 0 DC 5
VIN INP INN SIN( 0 100m 1k ) AC 1m
IBias VCC IAB 1m
R1 VCC INN 1k
R2 INN 0 1k
R3 VCC OUT 1k
R4 OUT 0 1k
XOTA LIN INP INN IAB OUT VCC BIN BUF HALF13700
R5 BIN OUT 1
R6 BUF 0 1000k
* The output can only swing withing a diode of the rails.
* The PNPL diodes have twice the voltage of the NPNs.
The LM13700 was designed to handle analog signals above the one volt peak range.
On a +/- 15volt application, the diode vbe voltage have little impact. While
a 5volt application can be done, extra care needs to directed at bias current
and signal voltage swings.